Date
23 May 2020
Webinar on VLSI Front End
Resource Person : Priya Anathakrishnan Corporate Technical Trainer
Date : 23rd May 2020
Time : 02.00 PM – 03.00 PM
Via : Zoom Meetings / YouTube
|
Activity Name |
VLSI Front End on 23-May-2020 |
|
Activity Type |
Lecture |
|
Conducted By |
CTDS Bangalore |
About the Activity
VLSI Design – Verilog Introduction
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using an HDL we can describe any digital hardware at any level. Designs, which are described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Presented by Mrs. Priya Ananthakrishnan, Corporate Technical Trainer & Former Senior VLSI Trainer, ChipEdge Technologies Pvt Ltd, Bangalore.
Events List
- Dr. A.C. Shanmugam Honored with Prestigious Doctorate by Mysore University
- Technical talk on Insights on Medical Device Regulatory Affairs and Quality Assurance
- Project Exhibition 2023
- Webinar on ORGANIC FARMING AND WASTE MANAGEMENT
- Workshop on “Products and Technologies Identification in MMSE sectors under Self Employment Opportunities”
- Mini-Project Exhibition
- Intra Institutional Internship Program Year 2022-2023
- Online Webinar on Health technology
- Technical Seminar on Bio Sensors
- Technical Talk on Case Studies on Application of Deep Learning in Healthcare Management & Autism